The fabrication of semiconductor wafers involves performing a number (tens or many tens) of processes on the wafer using a variety different tools, such as exposure tools, bake tools, etch tools, polishing tools, deposition tools, annealing tools, etc. A series of lithography steps are used to create patterned device features in previously deposited and processed layers. Between any two lithography steps, the intervening processes can affect the shape of the wafer. Yet, the wafer generally needs to be as flat as possible for many of the lithography processes, since a lack of flatness can result in a variation in the process as a function of position on the wafer. Such a variation is undesirable because it can lead to defects in the semiconductor devices (e.g. memory chips, logic chips, etc.) being fabricated in the wafer.
For example, if the process is a photolithographic process that involves printing lines for different exposure fields over the wafer, and the wafer has an amount of warpage that is comparable to the depth of focus of the photolithography tool, there can be a variation in the line widths formed over the different exposure fields on the wafer or even within a given exposure field. This variation can contribute to inadequate performance of the semiconductor devices being manufactured and can result in reduced yield.
Unfortunately, it is difficult if not impossible to know how a given processes contributes to the shape of a wafer. This is complicated by the fact that some semiconductor processes involve forming semiconductor structures on both the front-side and the back-side of the wafer.
While wafer flatness measurements can be made in a variety of ways, a very large number of (e.g., a million or more) measurements are needed to obtain adequate data to be able to make an assessment of the process contributions to the shape of the wafer. Interrupting the process flow to make such a large number of measurements has been generally considered impractical because it substantially reduces the throughput of wafers through the manufacturing process (i.e., reduces “throughput”), which results in a substantial increase in the cost-per-wafer.